1. Field of the Invention
The present invention relates to a constant-voltage circuit which is provided in a semiconductor integrated circuit to generate a constant voltage to be supplied to the internal circuit of the integrated circuit.
2. Description of the Related Art
Reference can be had to Japanese Patent Application Kokai No. H5-205469, Japanese Patent No. 2928531, U.S. Pat. No. 5,103,158 and U.S. Pat. No. 5,942,809.
FIG. 2 illustrates the configuration of a conventional internal supply-voltage generation circuit which is disclosed in Japanese Patent Application Kokai No. H5-205469 mentioned above.
The internal supply-voltage generation circuit is provided in a semiconductor memory device to generate an internal supply-voltage VINT from an external supply voltage VEXT. The internal supply-voltage generation circuit includes a reference voltage generation portion 50, a voltage sense portion 100, a latch portion 200, a reference-voltage control portion 300, and an internal supply-voltage generation portion 400.
The voltage sense portion 100 senses a voltage applied to a pad PAD, with a plurality of load transistors P1 to P4 and a resistor R1 connected in series between the pad PAD and a ground voltage VSS. Additionally, there is provided an inverter chain formed of inverters INV1 to INV3 at a connection between the transistor P4 and the resistor R1. The output terminal of the inverter INV2 is connected to the gate of a switching transistor N1, while one channel terminal of the transistor N1 is connected to the output terminal of the inverter INV3. The other channel terminal of the transistor N1 is connected to the latch portion 200.
The latch portion 200 has a resistor R2 connected to the external supply voltage VEXT and inverters INV4, INV5 for transmitting and latching the electric potential to be formed by the accumulation of current via the resistor R2. The latch portion 200 successively supplies the output signal thereof to the reference-voltage control portion 300.
The reference-voltage control portion 300 includes a transmission gate TM1 to be controlled with the output signal from the latch portion 200 and a pull-up transistor T1 connected to the output of the transmission gate TM1. The reference voltage generation portion 50 and an internal supply-voltage generation portion 40, which are known to those skilled in the art, are connected to the input and output of the transmission gate TM1, respectively.
When conducting a test on a memory circuit, for example, in a burn-in test, a high voltage is applied to the interior of such an internal supply-voltage generation circuit. For example, a predetermined voltage (e.g., the external supply voltage VEXT) is applied to the pad PAD. The input of the inverter INV1 in the voltage sense portion 100 is at level “H”, while the transistor N1 is turned on to output a level of “L.” This causes the latch portion 200 to provide an output signal at level “H.”
The transmission gate TM1 in the reference-voltage control portion 300 is thus turned off, thereby causing a reference voltage VREF from the reference voltage generator 50 to be interrupted. At this time, the gate of the transistor T1 is supplied with an inverted signal of the output signal from the latch portion 200 which has been inverted by the inverter INV6. This causes the transistor T1 to be turned on and the reference-voltage control portion 300 to output the external supply voltage VEXT, allowing the internal supply-voltage generation portion 400 to output the external supply voltage VEXT as the internal supply voltage VINT.
Now, during normal operation, i.e., when no voltage is applied to the pad PAD, the input of the inverter INV1 in the voltage sense portion 100 is at level “L”. This causes the transistor N1 to be turned off. The resistor R2 pulls up the input of the latch portion 200 to level “H,” allowing the latch portion 200 to provide an output signal of level “L.” Thus, the transmission gate TM1 in the reference-voltage control portion 300 is turned on, allowing the reference voltage VREF output from the reference voltage generator 50 to be transmitted to the internal supply-voltage generation portion 400. At this time, the transistor T1 is turned off. This causes the internal supply-voltage generation portion 400 to output an internal supply voltage VINT corresponding to the reference voltage VREF.
However, the conventional internal supply-voltage generation circuit has the following problems. That is, the gate of the transistor T6 in the internal supply-voltage generation portion 400, described as prior art, is supplied with the reference voltage VREF or the external supply voltage VEXT from the reference-voltage control portion 300 in accordance with the operation mode. The transistor T6 controls a bias current flowing through a differential amplifier. Thus, depending on the level of the reference voltage VREF, the internal supply-voltage generation portion 400 may not operate properly, thereby possibly preventing a desired internal supply voltage VINT from being obtained.